This invention relates generally to inverter-driven induction motor systems and, more particularly, to a dv/dt limiting circuit for controlling the rate of rise of inverter output voltage.
Adjustable frequency drives for controlling the speed of an induction motor are well known. Such drives often comprise a static inverter for converting a direct current (dc) input signal into an alternating current (ac) output signal having a frequency controllable by the user. These inverters may be of several types, one common type including power switching elements such as insulated gate bipolar transistors (IGBTs) gated by firing signals from a pulse width modulator.
However, such IGBT-based inverters generate rise rates in output voltage reaching up to 15,000 volts/.mu.sec. This shows up at the motor input as a high peak voltage, due in part to impedance mismatch between the motor and cable, combined with long cables connecting the motor and drive. While this may have a negligible effect at very short cable lengths, on relatively long cables the PWM pulses can act as impulse waves on the motor cable resulting in reflection phenomena. This can cause the peak voltage at the motor to approach a theoretical limit of two times. Such high peak voltages and the associated currents caused by high rise rates can have detrimental effects on the motor such as causing bearing failure or a failure in the motor windings. Large peak voltages occurring repeatedly over the cycle of the PWM waveform create stresses on the insulation of the motor stator winding. Also, a high frequency "ringing" waveform appears at the front and rear of each pulse, contributing to transient voltage amplitudes.
The dv/dt limiting circuit of the present invention addresses this problem by controlling inverter output to limit voltage rise rates to between 500 and 1500 volts/.mu.sec. This rise rate is low enough to allow reasonably long cabling between the inverter and motor without introducing the high peak voltages that would otherwise be introduced by the distributed inductance and capacitance inherent in the cable.
The present circuit is coupled between the inverter and motor and includes three capacitors connected in a delta configuration with each node connected between an inductor and a diode bridge rectifier input. Outputs from the bridge rectifier are passed through a resistor/capacitor circuit to return trapped energy to the inverter dc bus and to control peak output voltage. A large dc capacitor stores trapped inductor energy when an output contactor is opened.
These and other features and advantages of the present invention will become apparent upon review of the following specification taken in conjunction with the accompanying drawings.